1. Field of Invention
The present invention relates to a method of generating a reference voltage. More particularly, the present invention relates to a method and logic decision device for generating a ferro-electric capacitor reference voltage.
2. Description of Related Art
A conventional method of generating a reference voltage is to use a pair of dummy cells. FIG. 1 is a schematic circuit diagram for producing a reference voltage through a pair of dummy cells 102 and 104. If the dummy cell 102 has an operating voltage of V1 volts and the dummy cell 102 has an operating voltage of V2 volts, reference voltage of the structure in FIG. 1 is (V1+V2)/2 volts. In other words, a voltage greater than (V1+V2)/2 volts is designated as logic xe2x80x981xe2x80x99 and a voltage smaller than (V1+V2)/2 is designated as logic xe2x80x980xe2x80x99. However, since each capacitor has a slightly different electrical characteristic, the ferro-electric capacitor 110 inside the dummy cell 102 is charged at most to a voltage V3, where V3 less than V1. Similarly, the ferro-electric capacitor 112 is charged at most to a voltage V4, where V4 less than V2. Therefore, the actual reference voltage is (V3+V4)/2. A voltage V5 between the voltage (V1+V2)/2 and (V3+V4)/2, is smaller than (V1+V2)/2 and hence should be regarded as being at a logic xe2x80x980xe2x80x99. However, because of the capacitor property, the voltage V5 is actually compared with the reference voltage (V3+V4)/2. Since V5 is greater than (V3+V4)/2, this results in a logic xe2x80x981xe2x80x99. When this occurs, an incorrect logical decision between xe2x80x980xe2x80x99 and xe2x80x981xe2x80x99 is produced. Such erroneous logical decision due to a variation in ferro-electric capacitor property often leads to an edge effect.
Another conventional method of generating a reference voltage is to use a pair of different parasitic capacitors. FIG. 2 is a circuit diagram showing a method of deploying the voltage differential between a pair of different bit lines to produce a reference voltage. FIG. 3 is graph showing the variation between voltage and electric charge of the ferro-electric capacitor in the circuit shown in FIG. 2. The circuit shown in FIG. 2 is capable of a revolving edge effect due to a variation of capacitor property. Assume the bit line 204 has an overall length greater than the bit line 208; in other words, assume the parasitic capacitance 206 is greater than the parasitic capacitance 210. Also assume data electric charges Q1 waiting for logical decision sit inside the ferro-electric capacitor 202. First, the data charges Q1 waiting for logical decision is transferred to the parasitic capacitor 206 of the bit line 240. Since V=Q/C, a voltage V1 is produced. The charge/voltage inside the ferro-electric capacitor changes from point P1 to P2 following path A as shown in FIG. 3.
Thereafter, reference electric charges Q2 that represent logic xe2x80x980xe2x80x99 are stored inside the ferro-electric capacitor 202. The charge/voltage inside the ferro-electric capacitor change from P2 to P3 following path B as shown in FIG. 3.
Reference electric charges Q2 that represent logic xe2x80x980xe2x80x99 are stored inside the parasitic capacitor 210 generated by the bit line 208. The charge/voltage inside the ferro-electric capacitor changes from P3 to P2 following path C as shown in FIG. 3. Since V=Q/C, voltage produced by the parasitic capacitor 210 serves as a reference voltage V2.
After logical decision of the waiting data, the original electric charges Q1 waiting for a logical decision are returned to the ferro-electric capacitor 202. The charge/voltage inside the ferro-electric capacitor change from P2 to P1 via points P3 and P4 following path D as shown in FIG. 3.
Since V1 is greater than V2, the parasitic capacitor 206 is greater than the parasitic capacitor 210. Within a definite range, V1 is definitely greater than V2. That is, data logic xe2x80x981xe2x80x99 is quite obvious. Therefore, the method is very clear about the logic decision and is able to avoid edge effect problems due to a variation in capacitor property.
In brief, using identical ferro-electric capacitors for access but using a differential voltage due to the parasitic capacitor resulting from an extra length of between bit line 208 and 206 is able to avoid edge effect problem due to a variation in capacitor property. Within a definite range, logic level can be very accurately determined. Although edge effects can be avoided, other problems arise. The extra length in the bit line tends to increase volume occupation of the integrated circuit.
FIG. 4 is a schematic circuit diagram showing a system that uses an auxiliary device to produce a voltage differential and hence a reference voltage. Operating principals of the circuit are identical to the circuit shown in FIG. 2. The only difference is that an auxiliary device instead of bit lines of different overall length is used to generate the differential voltage. As before, the auxiliary device tends also to increase volume occupation of the integrated circuit.
In short, conventional methods of generating a reference voltage lead to the following problems:
1. Edge effects due to a variation of capacitor properties; and
2. Excessive volume occupation by the integrated circuit.
Accordingly, one object of the present invention is to provide a method of producing a reference voltage using ferro-electric capacitors so that problems in a conventional reference voltage provider such as edge effects and substantial volume occupation are reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of generating a reference voltage using a ferro-electric capacitor. A ferro-electric capacitor is charged so that the amount of electric charges within the ferro-electric capacitor is between the amount of electric charges for logic xe2x80x981xe2x80x99 and the amount of electric charges for logic xe2x80x980xe2x80x99. The electric charges are transferred to a capacitor so that a voltage is produced. The voltage produced by the capacitor is the reference voltage. The reference voltage is used to determine the logic level of data. The aforementioned ferro-electric capacitor and a ferro-electric capacitor for holding data waiting for a logical decision are identical.
This invention also provides a logic decision device that uses a reference voltage. The logic decision device includes a ferro-electric capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first bit line, a second bit line and a micro-sensor amplifier. The ferro-electric capacitor generates a reference voltage. The first transistor is coupled to the ferro-electric capacitor serving as a switch. The second transistor is coupled to the first transistor serving as a switch. The third transistor is coupled to the first transistor and the second transistor serving as a switch. The fourth transistor is coupled to the third transistor serving as a switch. The first bit line is coupled to the second transistor serving as a parasitic capacitor. The second bit line is coupled to the third transistor and the fourth transistor serving as a parasitic capacitor. The first bit line and the second bit line has an identical length. The micro-sensor amplifier is coupled to the first bit line and the second bit line for amplifying the micro-signal and performing a logical decision.
The reference voltage is generated by charging a ferro-electric capacitor so that the ferro-electric capacitor holds an amount of electric charges intermediate between logic xe2x80x981xe2x80x99 and logic xe2x80x980xe2x80x99. The electric charges are then transferred to a capacitor so that the capacitor produces a voltage. The voltage produced by the capacitor is the reference voltage.
Because the amount of electric charges producing the reference voltage is intermediate between logic xe2x80x981xe2x80x99 and logic xe2x80x980xe2x80x99, voltage at logic xe2x80x981xe2x80x99 and voltage at logic xe2x80x980xe2x80x99 are separated from the reference voltage by a clear voltage differential value. Furthermore, the same ferro-electric capacitor is used for producing the reference voltage and holding the data waiting for logic decision. Hence, logic level of data can be accurately determined and edge effect can be avoided.
Because the same ferro-electric capacitor is used for producing the reference voltage and holding the data waiting for logic decision and the amount of electric charges producing the reference voltage is intermediate between logic xe2x80x981xe2x80x99 and logic xe2x80x980xe2x80x99, voltage at logic xe2x80x981xe2x80x99 and voltage at logic xe2x80x980xe2x80x99 are separated from the reference voltage by a clear voltage differential value. Hence, there is no need to add any auxiliary device or use bit lines having different length to create a large voltage differential. Ultimately, size of the integrated circuit can be reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.